Logical circuit element comprising an mos field effect transistor



July 21, 1970 JEAN-PIERRE VASSEUR ETAL 3,521,081

LOGICAL CIRCUIT ELEMENT COMPRISING A MOS FIELD EFFECT TRANSISTOR 5Sheets-Sheet 1 Filed Nov. 30, 1966 Fig.3

y 1970' JEAN-PIERRE VASSEUR ETAL. 3,521,081

LOGICAL CIRCUIT ELEMENT COMPRISING A MOS FIELD EFFECT TRANSISTOR FiledNov. 30, 1966 5 Sheets-Sheet 2 MOS G G 2 v 92 9O 91 v A Fig.4 o *4 b lii I vs r; +v

July 21; 1970 3,521,031

LOGICAL CIRCUIT ELEMENT COMPRISING A MOS FIELD JEAN-PIERRE VASSEUR ETAL"EFFECT TRANSISTOR Filed Nov. 30. 1966 s Sheets-Sheet 5 y 1979 E."i AL3,52 ,081

LOGICEL CIRCUIT ELEMENT COMPRISING A MOS FIELD EFFECT TRANSISTOR FiledNov. 30, 1966 5 Sheets-Sheet 4 JICZ Mes

July.21, 1970 JEAN-PIERRE VASSEUR ETAL 3,

LOGICAL'CIRCUIT ELEMENT COMPRISING A MOS FIELD EFFECT TRANSISTOR FiledNov. 50, 1966 5 Sheets-Sheet 5 +4 Cp+5 MP Mp-kB MPH CF lM +z Fig.13

MP CP United States Patent 40,8 7 Int. Cl. H03k 19/08 U.S. CI. 307-20512 Claims ABSTRACT OF THE DISCLOSURE A logical circuit element comprisesat least one field effect transistor of the metal oxide semiconductor(MOS) type. An input connected to a two-level-voltage D.C. supply isconnected to its gate, and an input capacitor is series connectedbetween the input and the source. For a (first level the transistor isblocked, for the other it is unblocked. An output is connected to thedrain. An output capacitor is series connected between the drain and thesource. A pulse generator is connected to the output capacitor. Itcharges or not the output capacitor, according the level of the voltageapplied to the input. A diode prevents any discharge of the outputcapacitor across the MOS element.

The present invention relates to transistorized logical circuitelements.

According to the invention there is provided a logical circuitcomprising at least one field effect transistor of the metal oxidesemiconductor (MOS) type, having a source, a drain and a gate; an inputfor receiving signals connected to said gate, for blocking or unblockingsaid transistor; an input capacitor connected between said input andsaid source, and an output impedance connected in series between saidsource and said drain.

For a better understanding of the invention, reference will be made tothe drawings accompanying the following description and in which:

FIG. 1 represents the basic element of a circuit according to theinvention;

FIGS. 2 and 4 represent inverter elements;

FIGS. 3 and 5 are diagrams explaining'FIGS. 2 and 4;

FIGS. 6, 7, 8 and 9, show, respectively NOR, OR, AND and AND-NOTcircuits according to the invention;

FIGS. 10 and 12 represent, respectively, two embodiments of transferelements according to the invention;

FIG. 11 is an explanatory curve;

FIG. 13 shows an embodiment of a shift register according to theinvention; and

FIG. 14 is a curve explaining FIG. 13.

FIG. 1 shows a field effect element with insulated gate of the typesometimes referred to as the MOS (metal oxide semiconductor) fieldeffect transistor. The gate of the element is grounded through acapacitor C The source-drain circuit is mounted in series with acapacitor C a diode D and a pulse generator G.

The operation of the circuit is based on the following properties of MOSdevices:

(a) The grid biasing consumes practically no energy, the grid leak beingof the order of 10 ohms. If a low capacitance capacitor C is connectedbetween gate and earth, the same will not be discharged after thedisappearance of the gate voltage V It holds the memory of the voltage Vfor a long period.

(b) The MOS element operates as an interrupter.

In the state corresponding to the presence of a given Patented July 21,1970 ice gate voltage V the conductivity of the source-drain circuit isof the order of 1 millimho.

In the so-called blocked state, corresponding to the presence of a givengate voltage V the conductivity of the drain-source is reduced to 10-mho.

Thus, the operation of the arrangement of FIG. 1 is as follows:

It is assumed that the gate voltage V takes up the two values V and Vcorresponding to the two states of a binary logic, voltage Vcorresponding to the normal conduction and the voltage V to the blockedstate.

The generator G applying a short pulse to the terminals of capacitor Ctwo cases have to be examined:

(a) The gate voltage is V (capacitor C charged to V The MOS isconducting. The capacitor C is charged through the sourcedrain circuitto the voltage V (pulse amplitude). It will not discharge after thepassage of the pulse, because the diode D prevents any discharge.

(b) The gate voltage is V (capacitor C charged to V The MOS does notconduct. The capacitor C will not be charged.

Thus, once a pulse has been applied by generator G to the MOS element,there are two possible states of charge of the capacitor C whichrespectively correspond to the two states of charge of the capacitor CThe information stored at the terminals of capacitor C is thustransferred to the terminals of capacitor C If C '=C =C, the transfer ofinformation has been effected with an expense of energy W=CV with V ==VV which is very small, and much lower than in transistorizedmultivibrators.

Naturally, C may be replaced by an impedance Z. The same may comprise anelement with binary memory X. By means of the arrangement of FIG. 1, theinformation may be transferred from C to X.

FIG. 2 shows an inverter for a synchronous logical arrangement, derivedfrom the diagram of FIG. 1.

In the following description, it will be assumed that the MOS elementsare of the n-type. With p-type element, it is sufiicient merely toreverse the sign of the voltages applied and the direction in which thediodes conduct.

V will again designate the biasing voltage corresponding to the normalstate, and V the voltage corresponding to the blocked state.

FIG. 2 shows a depletion type MOS element. In other words, it isconducting for V1'=(] and blocked for V =V.

A capacitor C a first generator of positive pulses 50 and a diode D areconnected, as indicated, in series in the source-drain circuit.

A second positive pulse generator 70, a negative source of DC. voltage Vand a diode D are connected in parallel with the capacitor C and thegenerator 50.

The gate circuit comprises a capacitor C whose terminal A is connectedto a fixed voltage source 80.

The transfer of information is effected from the point G where the gridpotential is measured, to point G the output of the diode D The processis a follows:

With the capacitor C discharged, the voltage -V is applied at the pointB to the terminal of the diode D At the moment T (FIG. 3), a shortpositive pulse, whose crest is +V, is applied to the point A by thegenerator 50. Two cases have to be considered:

(a) The potential at G, is zero, the MOS element is conducting, thecapacitor C is charged with the voltage +V. At the end of the pulse, thepotential at A becomes again zero; the voltage at G is then equal to V.

(b) The potential at G, is equal to V, the MOS element is notconducting, the capacitor C is not charged. At the end of the pulse, thepotential at G is zero.

n the generator 70 The capacitor C is discharged, whe applies a'positive pulse'to B 4 b FIG. 4 shows another embodiment of theinvention. The MOS element'is of the enhancement 'type,-whereintheblocking voltage is 'zero andits'conducting voltage is i-vfThecapacitor C is mounte d between the gate and earth. "A'diodd D ismounted inj the sourc'e 'circuit and conducts in the direction from thesource to point D.

A second diode D is mounted'in thedrain circuit and conducts in thedirection from the pointA to the drain.

Similarly, a third diode' D is mountedbetween' the drain and the point Band conducts from the. drain to point B. The capacitor C is mountedbetween the drain and'earth. The information is transmitted fromj thepointG (gate) to the point Gg (drain l I J FIG. "5 shows the voltages V'V andV whichar e respectively appliedto points A, B and D, by pulsegenerators 90, 91, 9 2." Y

The operation of the circuit is as follows: the MOS element is blockedwith zero gate potential and unblocked with a potential of +V.

The capacitor C is discharged. A positive pulse, with a peak value equalto +V, is applied at the instant T at point A, by pulse generator 90;since the point D is normally at a potential V applied by pulsegenerator 2, a negative pulse V, synchronized with the former, reduce itto zero.

Two cases are possible:

(a) The potential at point G is Zero. The MOS element is not conducting.The pulse charges the capacitor C through the diode D to the potentialV. G =V.

(b) The potential G is equal to +V. The MOS element is conducting. Thecapacitor C is short-circuited by a weak resistance (that of the MOSelement) and is not charged: 6 :0.

The diode D serves to discharge the capacitor C at the end of the cycleby means of a negative pulse which is applied to point B at the time TThe elements according to the invention can be grouped in series or inparallel to build up various logical function circuits.

The input impedance of a MOS element is, in fact, formed by a very highresistance in parallel with a weak capacitance.

It follows that several inputs can be coupled in parallel.

Similarly, the output impedance of a blocked MOS element is very highand it is possible to connect without difficulty a large number ofoutput circuits in parallel to a single capacitor. v

FIG. 6' shows a circuit which shown in FIG. '2.

It comprises two elements'MOS and MOS' whose respective drain areconnected to the diode D and whose sources are connected to earth. Theirgates are, respectively, connected to capacitors C C The two inputs areat points G 'G JThe diodes D D and the capacitor C are mounted as shownin FIG. 2. It suffices that one of the MOS elements should conduct,i.e., that points G or G should beat a zero potential to obtain '-'-V atpoint G The presence'of the information 0 at one input results in thepresenc'e'of this information 1 at the output.

*FIG; 7"repres'ent'san OR circuit. Thiscircuit is developed fromthat'ofFIGJ 6' byadding a third circuit comprising an 'MOS element;identical toth'at' of FIG. 2. The pulse generatorsare 501, 701', 502,702.

An information present 'at'Gn or G is found at G and can be madeavailable at G2 FIG. 8 shows an 'AND circuit. The samecon'sists of acircuit'III such as that shown in FIG; '6," to 'the'inputs of which areconnected two circuits I and II, such as shown inFIG.2.'

is derived from the circuit '-I-he""circuit of FIG. 9 is a NORcircuitJIt comprises two elements M08 and MOS in seriesbetween'earth andthe diode D i The alisencebfinformation in*"the assembly preventsany'c'onductionof the group M05 M08 Conduction takes-pla'Ce-"onlynah-ere i'san'information at-the tWO eIGme T tS-" ""FIG. l o 'sh'dws "a'so called"tI'aIiSferelemHt It Cornpr'i'ses aninput G -"a'nd adoutputGglThe inputG is connected to the gate-crannies, element, the source" ofwhich isearth'edJA diodeD is-mounted in bridge circuitbetween the drainan'dthe source.

. It"'conducts in the-direction from the earth to the dr ain.

L A capacit'ofGI conn'ects'the drain to the output 65. Two points "A andB are connect'edbetween the point G and 'a pulse generator-bytwodiodes,Dg and- D respectively. Diode D -isin the same direction as D diode D inthe opposite sense. i

-The operation of the arrangement may 'be understood with reference toFIG. 11, which is concerned with an -enhancerhen typ'e' element. v l

?; Point 'A is normally at zeropotential and pulse's'ource 100applies-thereto pulsewith the cr st'-| -V at the moment T .Two casesmay'occuru- (a) At the moment izT the potential of-point G is +V,and-the" MOS- element is conducting. The capacitor C is charged by thepulse passing through the diode D the capacitor C and the MOS element.Point G assumes the potential '|-'."V. a I

(b) The potential of G is zero. The MOS element does not conduct. Thecapacitor C is not charged. Its potential remains zero.

At the moment T a negative pulse-discharges the capacitor C The diode Dfixes the potential of the armature of the capactior C connected .to theMOS element When the latter is blocked, This. diode can be incorporatedinto the MOS element. In this case, it is formed by the junctionbetweenthe drain and .the body of the semiconductor. 7 v

In this drawing, an enhancement type element has been used. In the case.of a depletion type element, it is sufficient to offset the voltage atA and B by a fixed value corresponding to the used element.

A. modification is shown in FIG. 12. In this diagram, the diode D hasbeen replaced by an element MOS blocked during the positive pulseapplied at A and conducting during the remainder of the time. To thisend, the gate of the element is connected to a point F held at asuitable potential. The source and the drain of the M05 element areconnected, respectively, to the source and to the drain of theMOSelement. Owing to the presence of the MOS element, the inputimpedance ofthe unit, as seen from the. point H, i s,low, which facilitates thesetting up of a sequence of elements. If, in factthe junction point oftwo consecutive elementsis at the point H, the danger of deteriorationby leakage currents is eliminated.

It has. thus been shown that, due to the circuits of FIGS. IO'and 12,the voltage atpoint G is transported to pointG after the application ofthecontrol pulse. This is the rea sonf why'such circuits are designatedas'transfer circuits' 'lheylcan be used in making shift registers.

The shift register "of FIG. 13 comprises a number of stages, some ofwhich are shown inFIG." 13 at M to M Each of these stages'isddentical'to the fcireuit wn n IG- y. I 1- he ut p qfj c' th e S e he n ut of thenext-sta e. I

A clock, not shown, supplies four distributionpoints A, B, and A, B.

'The'piilses for charging and discharging the capacitors C C aredelivered, respectively,"'by the points A, B. The pulses for' chargingand dischargingthe capacitors C andC are delivered by the points A, B,respectively.

The voltages at A, A, B, B are represented in FIG. 14.

The capacitors C C are charged at the time T T The capacitors C C arecharged at the time T ,T.;. 1

The discharges take place, respectively, at the time T' T'3 and T z, Tg.

The instants T and T' are offset in time by the width of one pulse. Thecontrol voltages of the register are recovered at the points M At thestart, all volt ages'are zero, with the exception of one which is equalto V..

The voltage +V progresses at every sequence of pulses of the clock fromM to M Thus, at a given instant, only one gate is open, except duringthe switching periods.

Of course, the invention is not limited to the embodiments described andshown which were given solely by way of examples.

What is claimed, is:

1. A logical circuit element comprising at least one field-effecttransistor of the meal oxide semiconductor (MOS) type, having a source,a drain and a gate; an input for receiving signals connected to saidgate, for blocking or unblocking said transistor; an input capacitorconnected between said input and said source; an output terminal, meansfor connecting said output terminal to said drain, output capacitancemeans connected to said output terminal; a first pulse generatorconnected to said output capacitance means and a first diode in seriesbetween said drain and said source, for preventing the discharge of saidoutput capacitance means across said MOS, when conductng.

2. A logical circuit as claimed in claim 1, wherein said outputcapacitance means is a capacitor.

3. A logical circuit element as claimed in claim 2, wherein said firstdiode is connected in series between said output terminal and saiddrain.

4. A logical circuit element as claimed in claim 3, further comprisingmeans for connecting a source of voltage between said source and saidinput capacitor; 3 second positive pulse generator and a second diodefor conducting said second positive pulses connected in series between asource of negative DC. potential and said output terminal, said secondpositive pulses having the amplitude of said negative DC. voltage.

5. A logical circuit element as claimed in claim 4, further comprising asecond MOS transistor, having its drain source circuit connected inseries to said source; said second MOS having a second input terminal, asecond gate connected to said second input terminal, and a second inputcapacitor connected to said second gate, and means for connecting asecond source of DC. potential between said second input capacitor andsaid second source.

6. A logical circuit element as claimed in claim 2, wherein said firstpulse generator and said first diode are series connected between saidsource and said drain, further comprising: a third pulse generator forgenerating third pulses of the same amplitude and of the opposite.polarity to that of said first pulses, at the same instants said drain,said output capacitor being connected between said source and drain.

7. A logical circuit element as claimed in claim 2, wherein said outputcapacitor is series connected between said drain and said outputterminal; an eleventh diode being connected between said drain and saidsource, for conducting the current between said source and said drain, atwelfth diode and said first diode being oppositely mounted, andconnected to said output terminal; said first pulse generator and atwelfth pulse generator for generating pulses of a polarity opposite tothat of said first pulses, being connected to said first diode and saidtwelfth diode respectively.

8. A logical circuit as claimed in claim 7, further comprising a'secondMOS having second drain and source parallely connected with said drainand source of said first MOS, and a second gate, connected to a fixedpotential.

9. A plurality of circuits as claimed in claim 8, cascade connected, theinput terminal of one circuit being connected to the output terminal ofthe following one, and means for applying successive pulses to saidinput terminals of said circuits in succession.

10. A logical circuit element as claimed in claim 1 further comprising asecond transistor having a second input terminal, a second gateconnected to said second input terminal, a second input capacitorconnected between said second gate and second source, a second drainconnected to said drain and a second source connected to said source.

11. A logical circuit as claimed in claim 10, further comprising a thirdMOS transistor having a gate connected to said output terminal, afurther output terminal, a source and a drain, a further outputcapacitor, a seventh positive pulse generator for applying seventhpositive pulses to said further output capacitor, and a seventh diode,said seventh diode and said further capacitor being connected in seriesto said drain; an eighth pulse generator for applying eighth positivepulses to said further output terminal and an eighth diode for passingsaid last mentioned pulses.

12. A logical circuit as claimed in claim 10, further comprising a fifthand a fourth MOS transistor, having further respective input terminalsand respective gates connected respectively to said further respectiveinput terminals, a ninth positive pulse generator for applying positivepulses to said output capacitor, a ninth diode for passing said pulsesto said source, a tenth positive pulse generator for applying pulses tosaid gate of said fifth and sixth MOS transistor, and a tenth diode forpassing said pulses.

References Cited UNITED STATES PATENTS 5/1966 Weimer 307-221 3/1968Lambert 307-304X US. Cl. X.R.

